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Singh, Kamaljeet
- Comparative Study of Jam Preparation from Various Cultivars of Mango and Mango - Papaya Blends
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Authors
Affiliations
1 Division of Post Harvest Technology, Faculty of Agriculture, Sher-e-kashmir University of Agricultural Science and Technology (J), Chatha, Jammu, J&K, IN
1 Division of Post Harvest Technology, Faculty of Agriculture, Sher-e-kashmir University of Agricultural Science and Technology (J), Chatha, Jammu, J&K, IN
Source
International Journal of Processing and Post harvest Technology, Vol 4, No 1 (2013), Pagination: 18-25Abstract
A comparative study on preparation of jam from three mango cultivars viz., Dashehari, Totapuri and Desi in combination with papaya was undertaken. The mango and papaya pulps were blended in the ratio of 100:00, 85:15, 70:30 and 55:45. Jams were prepared as per FPO specifications in which TSS was raised to a minimum of 68.50B by adding sugar and acidity was maintained at 0.6 per cent using citric acid. Jams prepared were stored under ambient condition in glass containers and subjected to physico-chemical analysis at two months interval for a period of six months. The highest TSS (69.780B), total sugars (64.72%), reducing sugars (32.46%) and total carotenoids (7.60 mg / 100 g) were recorded in T10(Desi), whereas maximum acidity (0.652%), pectin (0.87%), dry matter (75.44%) and ash (3.27%) were recorded in T6 (Totapuri). The maximum ascorbic acid content of 23.79 mg/ 100 g was found in T13 (Desi + Papaya; 55:45) and minimum in T6 (Totapuri). During storage, an increasing trend was observed in TSS, total sugars and reducing sugars, whereas acidity ascorbic acid, total carotenoids, pectin and ash decreased. The storability study revealed that jams were of good shelf life and can be kept at least for six months without affecting the quality attributes.Keywords
Jam, Mango, Papaya, Blends, Cultivars
- Development of High Density through the Wafer Vias Using Drie Based Micromachining
Abstract Views :155 |
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Authors
Affiliations
1 Semi-Conductor Laboratory, Chandigarh, IN
1 Semi-Conductor Laboratory, Chandigarh, IN
Source
Manufacturing Technology Today, Vol 14, No 3 (2015), Pagination: 16-20Abstract
Fabrication of deep silicon vias in silicon for the feasibility of three dimensional (3-D) MEMS structures faces multiple technological process challenges before it can become a commercially viable technology. One of the key fabrication step required is the deep silicon etching for forming high aspect ratio structures. This technology can be easily integrate in the conventional process flow during siliconization of the device. There is an increasing interest among the researchers in the use of dry plasma etching for this application because of its anisotropic etching behavior, high etch speed, good uniformity, profile control and high aspect ratio capabilities without causing any undesired secondary effects. In-house high-density through-wafer vias process is being developed at Semi-Conductor Laboratory. The aim is to achieve cost-effective vertical interconnects CMOS compatible that are easily integrated into a device process flow. Deep reactive ions etch (DRIE) process was developed to etch 50 μm dia via holes through 675 μm thick silicon wafers. The DRIE BOSCH process was optimized to carry out through and through via holes in silicon. Further, a thin gold (Au/Ti) metal layer was deposited as a seed layer in the vias and afterwards these vias Au layer filling is carried out using the electroplating technology to be used as conductive material. A novel in house process was developed using DRIE for achieving the desired aspect ratio of 14:1 required for realization of high density via holes. Detailed process steps are discussed in this article which can be utilized for various via dimensions as per the application requirements. Also role of various parameters and its effects are given in this article.Keywords
Through-Wafer Vias, Dry Etching, Deep Reactive Ion Etching, DRIE, 3-D Microsystems, Aspect Ratio, SEM.- Characterization and Mitigation of Electro-Static Bonding Failures in Microsensors
Abstract Views :184 |
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Authors
Affiliations
1 Systems Engineering Group, ISRO Satellite Centre, IN
1 Systems Engineering Group, ISRO Satellite Centre, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 1 (2017), Pagination: 345-348Abstract
Electrostatic bonding between glass and silicon is carried out in micro sensor devices to achieve higher bond strength thus eliminating the requirement of adhesives. This can also be useful in providing hermiticity and results in reliable operation of the micro sensor devices. Practically the sensor performance is prone to long term drift mainly due to process associated with the assembly and packaging. Bonding is the one of the critical process in micro sensor and generally sensor stability is dependent on this process along with other packaging material and methodology. Bond strength is one of the critical parameters to find out the quality of bond and the same is quantified and compared for different conditions. This article details electrostatic bonding process, various parameters responsible for the reliable bonding, modelling and characterization along with simple methodology to achieve higher bond strength.Keywords
Bonding, Micro-Sensor, Anodic, Electrostatic, Sensor, Bond Strength.References
- Kamaljeet Singh and A.V. Nirmal, “Reliability Aspects in RF-MEMS Circuits for Space Applications”, Journal of Engineering and Technology Research, Vol. 4, No. 6, pp. 1-11, 2016.
- W.H. Ko, J.T. Suminto and G.J. Yeh, “Bonding Techniques for Microsensors”, Proceedings of Conference on Micromachining and Micropackaging of Transducers, pp. 41-61, 1985
- Mohamed Gad-el-Hak, “The MEMS Handbook”, 2nd Edition, CRC Press, 2002.
- K. Petersen, P. Barth, J. Poydock, J. Brown, J. Mallon and J. Bryzek, “Silicon Fusion Bonding for Pressure Sensors”, Proceedings of IEEE Solid State Sensor and Actuator Workshop, pp. 144-147, 1998.
- Hyun S. Kim, Robert H. Blick, D.M. Kim and C.B. Eom, “Bonding Silicon-on-Insulator to Glass Wafers for Integrated Bio-Electronic”, Applied Physics Letters, Vol. 85, No. 12, pp. 2370-2373, 2004.
- R. Knechtel, G. Dahlmann and U. Schwarz, “Low and High Temperature Silicon Wafer Direct Bonding for Micromechanical Absolute Pressure Sensor”, Proceedings Electromechanical Society, pp. 205-207, 2005.
- G. K. Ananthasuresh, K.J. Vinoy, S. Gopalakrishnan, K.N. Bhat and V.K. Aatre, “Micro and Smart Systems”, Wiley, 2010.
- Contaminations in MEMS Processes and Removal Methodology
Abstract Views :199 |
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Authors
Affiliations
1 Systems Engineering Group, ISRO Satellite Centre, IN
1 Systems Engineering Group, ISRO Satellite Centre, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 1 (2017), Pagination: 375-378Abstract
Wafer impurities and process particulates are one of the prime reason of MEMS device failure. Various cleaning methodologies are evolved but cleaning remains a critical process in MEMS domain as varied materials along with micromachining operations are involved. Bulk and surface micromachining process results in etching of substrate as well as various layers which necessitate evolving of proper cleaning methodology to avoid device failure. This article details the sources of contamination, role of contamination in MEMS domain, cleaning and measurement techniques to mitigate the effect on the device performance.Keywords
MEMS, Contamination, Residues, Particulates, Defects.References
- Rajiv Kohli and K.L. Mittal, “Developments in Surface Contamination and Cleaning”, 1st Edition, Elsevier, 2014.
- Gary K Feeder, “MEMS Fabrication”, Proceedings of IEEE-ITC International Test Conference, pp. 691-698, 2003.
- Mohamed Gad-el-Hak, “The MEMS Handbook”, 2nd Edition, CRC Press, 2002.
- G.K. Ananthasuresh, K.J. Vinoy, S. Gopalakrishnan, K.N. Bhat and V.K. Aatre, “Micro and Smart Systems”, Wiley, 2010.
- Janusz Bryzek, “Principles of MEMS: Handbook of Measuring System Design”, John Wiley and Sons, 2011.
- Werner Kern, “The Evolution of Silicon Wafer Cleaning Technology”, Journal of Electrochemical Society, Vol. 37, No. 6, pp. 1887-1892, 1990.
- Chandan Kumar Sarkar and Sunipa Roy, “MEMS and Nanotechnology for Gas Sensors”, CRC Press, 2015.
- Kamaljeet Singh and A.V. Nirmal, “Reliability Aspects in RF-MEMS Circuits for Space Applications”, Journal of Engineering and Technology Research, Vol. 4, No. 6, pp. 1-11, 2016.
- J. Grym, “Semiconductor Technologies”, InTech Publisher, 2010.
- Overview of MEMS Sensors and Associated Aspects
Abstract Views :209 |
PDF Views:6
Authors
Affiliations
1 Systems Engineering Group, ISRO Satellite Centre, Bangalore, IN
1 Systems Engineering Group, ISRO Satellite Centre, Bangalore, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 2 (2017), Pagination: 411-416Abstract
MEMS technology is pervading in all domains ranging from commercial to strategic sectors so it is imperative that application oriented development encompassing fabrication, characterization, assembly and packaging aspects to be looked into to get the reliable product. This article details the overview of MEMS sensors and various aspects such as thin film process, process characterization tools, assembly along with challenges in realization are presented. Reduction in measurement inaccuracy is extremely important and main parameters associated with the sensors are explained.Keywords
MEMS, Sensors, Fabrication Process, Assembly.References
- G.K. Ananthasuresh, K.J. Vinoy, S. Gopalakrishnan, K.N.Bhat and V.K. Aatre,“Micro and Smart Systems”, Wiley India, 2010.
- Sunipa Roy and Chandan Kumar Sarkar, “MEMS and Nanotechnology for Gas Sensors”, 1st Edition, CRC Press 2016.
- Kamaljeet Singh, “Substrate Material Considerations in MEMS Processes for RF Applications”, Nano and Microsystems Technology, Vol. 19, No. 7, pp. 428-431, 2017.
- Kamaljeet Singh and A.V. Nirmal, “Reliability Aspects in RF-MEMS Circuits for Space Applications”, Journal of Engineering and Technology Research, Vol. 4, No. 6, pp. 1-11, 2016.
- Amit Saxena, Satya N Behera, Kamaljeet Singh and Paritosh Jain, “Process Optimization and Role of Process Parameters for Repeatable Metal Etching”, Proceedings of National Conference on Micro and Nano Fabrication, pp. 1-4, 2013.
- R Osiander, M.A.G. Darren and J.L. Champion, “MEMS and Microstructures in Aerospace Applications” , 1st Edition, CRC Press, 2005.
- Janusz Bryzek,“Principles of MEMS: Handbook of Measuring System Design”, John Wiley and Sons, 2011.
- Kamaljeet Singh, A.V. Nirmal and S.V. Sharma, “Investigation of Drift Phenomena Observed in Platinum Thin Film based Temperature Sensor for Metrological Applications”, Proceedings of 2nd National Conference on Recent Developments in Electronics, pp. 12-16, 2017.
- Kamaljeet Singh and A.V. Nirmal, “Development and Characterization of RF-MEMS Shunt Switch at Ka-Band”, Proceedings of 8th International Conference on Smart Materials, Structures and Systems, pp. 31-32, 2017.
- N. Yazdi, F Ayazi and K Najafi, “Micromachined Inertial Sensors”, Proceedings of IEEE, Vol. 86, No. 8, pp. 1640-1657, 1998.
- Jan Grym, “Semiconductor Technologies”, InTech Publisher, 2010.
- Mohamed Gad-El-Hak, “The MEMS Handbook” , 1st Edition, CRC Press, 2002.
- P. Malshe, W.D. Brown, W.P. Eaton and W.M. Miller, “Challenges in the Packaging of MEMS” , International Journal of Microcircuits and Electronic Packaging, Vol. 22, No. 3, pp. 233-241, 1999.
- Link Margin for Wireless Radio Communication Link
Abstract Views :215 |
PDF Views:4
Authors
Affiliations
1 Systems Engineering Group, ISRO Satellite Centre, Bangalore, IN
1 Systems Engineering Group, ISRO Satellite Centre, Bangalore, IN
Source
ICTACT Journal on Communication Technology, Vol 8, No 3 (2017), Pagination: 1574-1581Abstract
The systematic evaluation of the link budget calculation for the satellite and terrestrial communication is presented in this article. Communication link between the satellite and earth station is dependent on various propagation and associated losses which are either constant or vary with weather conditions. Role of receiver noise, antenna pointing mechanism, atmospheric effects, slant height, interferences, bit error rate on the link margin are detailed in this article. Various equations for link budget calculation and a comparative table at various frequency bands are shown in this article which is useful for predicting link margin of LEO, GEO and Deep space missions. Tele-command, telemetry and ranging link margin at various frequencies are presented and budget analysis at Ka-band frequency performed.Keywords
Link Budget, Margin, Atmospheric Effects, Noise, Propagation Losses, Uplink, Downlink.References
- D.M. Pozar, “Microwave Engineering”, John Wiley and Sons, 2010.
- S.K. Sharama, S. Chatzintos and B. Otersten, “In-line Interference Mitigation Techniques for Spectral Coexistence of GEO and NGEO Satellites”, International Journal of Satellite Communications, Vol. 34, No. 1, pp. 11-39, 2016.
- V Sambasiva Rao, “Extend LEO Downlinks with GEO Satellites”, Available at: http://www.mwrf.com/datasheet/extend-leo-downlinks-geo-satellites-pdf-download.
- Aderemi A. Atayero, Matthew K. Luka and Adeyemi A. Alatishe, “Satellite Link Design: A Tutorial”, International Journal of Electrical and Computer Sciences, Vol. 11, No. 4, pp. 1-6, 2011.
- C. Haslett, “Essentials of Radio Wave Propogation”, Cambridge Wireless Essentials Series, 2008.
- R. Ashiya, “A Regional Satellite System for Mobile Communications”, Proceedings of IEEE International Conference on Personal Wireless Communications, pp. 142-146, 1994.
- K.N. Madhavan, D. John, A. Bhaskaranarayana,T.S. Narayan, M. Rathnakumar, V.K. Lakshmeesha and S. Pal, “TT&C Transponder for INSAT-2 Series Satellites”, IETE Technical Review, Vol. 11, No. 5, pp. 291-296, 1994.
- W.S. Cheung and F.H. Leuvien, “Microwave Made Simple”, Artech House, 1995.
- T.C. Barbosa,R.L. Moreno,T.C. Pereira and L.H.C. Ferreira,“ FPGA Implementation of a Reed Solomon Codec for OTNG.709 Standard with reduced Decoder Area”, Proceedings of 6th International Conference on Wireless Communications Networking and Mobile Computing, pp. 1-4, 2010.
- Daniel Minoli, “Innovations in Satellite Communications Technology”, Wiley, 2015.
- L.S Chuan, S.R-Tian andY.P Hon, “Ka-Band Satellite Communications Design Analysis and Optimisation”, DSTA Horizons, pp. 70-78, 2015.
- S. Dey, D.K. Mohapatra and S.D.R.P. Archana, “An Approach to calculate the Performance and Link Budget of LEO Satellite (Iridium) for Communication Operated at frequency Range (1650-1550)MHz”, International Journal of Latest Trends in Engineering and Technology, Vol. 4, No. 4, pp. 96-103, 2014.
- Semi-Conductor Ambience For Building Self-Reliance in the Country
Abstract Views :169 |
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Authors
Affiliations
1 Systems Engineering Group, ISRO Satellite Centre, Bangalore, IN
1 Systems Engineering Group, ISRO Satellite Centre, Bangalore, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 4 (2018), Pagination: 488-493Abstract
In the present era of importing chips are the major bottlenecks in attaining self-reliance for the strategic sector in the country. The existing trend of chip development at nanometer geometry needs huge and constant capital investment which is not possible in present scenario. The requirement of the country is to have maximum and efficiently utilization of available technology which can cater for achieving self-reliance in strategic sector requirements. Further effort towards miniaturization and multiple operations using single chip solution can put country on the world map. The major bottlenecks in the country are the fabrication and realization of such systems which can leads to self-reliance in the country. In spite of the whole hearted support of the government still we are far behind in achieving self-sufficiency with the available technology node. Some of the industries closed their manufacturing operations and remaining are not performing as per expectations. In spite of leaders in chip design and flooded with best talent still we are way behind self-reliance in the area of semiconductor in spite of huge investments. This article will bring out the foundry complexity, present scenario in the country, corrective methodology, and suggestive framework for creating semiconductor ambience in the country.Keywords
Semiconductor Industry, Self-Reliance, Technology Upgradation, Integrated Circuits.References
- Pratik A Joshi, “Indian Electronics Industry-A Persuasive Growth Engine behind the Soaring Economy of India”, International Journal of Education Economics and Development, Vol. 1, pp. 1-5, 2015.
- S. Das, “The Indian Electronics Industry in 2017-18: Key Opportunity and Trends”, Available at: http://www.electronicsb2b.com/eb-specials/industry-report/indian-electronics-industry-2017-18-key-opportunities-trends/
- H. Kushwah and A. Seth, “Future of Semiconductor Fabrication Industries in India-Opportunities and Challenges”, International Journal of Research in Engineering and Technology, Vol. 4, No. 8, pp. 72-75, 2015.
- Dipayan D Chaudhuri, “Technology Transfer and In-House R and D in Indian Electronics Industry under Economic Liberalization”, Allied Publishers, 1999.
- ITRS Report, Available at: http://www.itrs2.net/itrs-reports.html, Accessed on 2015.
- Kamaljeet Singh, “Major Steps in Thin Film Process and Overview of Various Resources”, Antriksh Gyan Sarita-Annual Magazine, Vol. 1, pp. 84-89, 2015.
- Kamaljeet Singh and A.V. Nirmal, “Technological Advancement by Bridging the gap between Industry and Academia”, Proceedings of 5th International Conference on MOOCs,Innovation and Technology in Education, pp. 11-15, 2017.
- Kamaljeet Singh and A.V. Nirmal, “Reliability Aspects in RF-MEMS Circuits for Space Applications”, Journal of Engineering and Technology, Vol. 4, No. 6, pp. 1-11, 2016.
- Kamaljeet Singh and A.V. Nirmal, “Growth Model of ISRO Growth in Indian Perspective”, Proceedings of 5th International Conference on Emerging Trends in Engineering, Technology, Science and Management, pp. 563-568, 2017.
- W. Schaufeli and A. Bakker, “Work Engagement Scale”, Preliminary Manual, Utrecht University, 2004.
- B.K. Bahinipati, “A Frame Work for Semiconductor Industry Supply Chain Planning”, International Journal of Intelligent Enterprise, Vol. 1, No. 3-4, pp. 290-314, 2012.
- Overview of Modulation Schemes Selection in Satellite based Communication
Abstract Views :185 |
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Authors
Affiliations
1 Systems Engineering Group, U R Rao Satellite Centre, Bangalore, IN
1 Systems Engineering Group, U R Rao Satellite Centre, Bangalore, IN
Source
ICTACT Journal on Communication Technology, Vol 11, No 3 (2020), Pagination: 2203-2207Abstract
Satellite based communication either in GEO or LEO based system are prominently employed for voice, video, data communication. Demand of more traffic necessitates the data rate of satellite to be enhanced which can be implemented by the proper choice of modulation scheme. Presently ground systems are also wireless based which include direct broadcast satellite (DBS),television service, wireless local area networks (WLANs), global positioning satellite (GPS), radio-frequency identification systems which is either point-to-point or point-tomultipoint. Modern day communication systems are digital; based rather than analog to have better noise immunity. Further with the limited spectrum availability the choice of modulation scheme plays an important role for faithful transmission of the signal. The digital communication can be categorized as Amplitude Shift Keying (ASK), Frequency Shift Keying (FSK), Phase Shift Keying (PSK) whereas for higher bit data rate Phase Shift Keying (PSK) such as BPSK, QPSK and OQPSK are employed. This article overview of various modulation schemes which are employed in satellite communication apart from its selection criteria along with the concept of bit error rate.Keywords
Modulation Scheme, Communication System, Noise, Radio-Frequency.- Process and Modelling Aspects of Polyimide Over Silicon for RF Circuits Realization and its Implementation
Abstract Views :143 |
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Authors
Affiliations
1 U R Rao Satellite Centre, Indian Space Research Organisation, IN
1 U R Rao Satellite Centre, Indian Space Research Organisation, IN
Source
ICTACT Journal on Microelectronics, Vol 5, No 1 (2019), Pagination: 711-714Abstract
The integration of RF circuits with CMOS on the same substrate is challenging and imposes lot of constraint in practical realization due to inherent losses associated with silicon Si substrate. Various mitigation techniques are proposed to overcome the same which are either process intensive or introduces multiple deleterious effects at RF frequencies. Polyimide is used both in microelectronics and MEMS industry as it can act both as a photo-resist and also having key dielectric properties. The processes presented with polyimide are standard and can be easily integratable with the existing CMOS processes. Fabrication steps and simulation study of the band pass filter topologies over polyimide are presented and the same are fabricated with the proposed process steps. Further this article details the modelling, theoretical aspects, various process steps and actual implementation with the realization of the band pass filter topology using the proposed methodology.Keywords
Polyimide, Silicon, Radio Frequency, Modelling.- RF Circuit Realisation Using Thick Film Technology
Abstract Views :143 |
PDF Views:0
Authors
Affiliations
1 Systems Engineering Group, U R Rao Satellite Centre, IN
2 HMC and Indigenization Group, U R Rao Satellite Centre, IN
1 Systems Engineering Group, U R Rao Satellite Centre, IN
2 HMC and Indigenization Group, U R Rao Satellite Centre, IN
Source
ICTACT Journal on Microelectronics, Vol 7, No 2 (2021), Pagination: 1115-1120Abstract
Thick film technology is mostly employed at lower frequency circuits such as hybrid micro circuits due to the associated losses of the paste. The characterisation and implementation of the conductive paste at higher frequencies is important so as to employ this technique at higher frequencies. Also the role of ceramic substrate due to higher dielectric losses needs detailed measurement to deduce the useful range of this technique with the selected paste. In this article simple transmission line using the thick film technology is fabricated, characterised and result of the thick and thin film technologies are compared. Subsequently RF circuits such as filter are fabricated using both thick and thin film fabrication technology and comparative analysis carried out. The line losses of 0.01 dB/cm up till 5 GHz is achieved using the standard gold paste. This article details the fabrication process, implementation methodology, design aspects, simulation and comparative analysis of the microstrip circuits such as transmission line and band pass filter.Keywords
Thick Film, Microstrip, Band Pass Filter, Transmission Line.References
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